• DocumentCode
    3361230
  • Title

    1/5 power reduction by global optimization based on fine-grained body biasing

  • Author

    Nakamura, Yasumi ; Levacq, David ; Xiao, Limin ; Minakawa, Takuya ; Niiyama, Taro ; Takamiya, Makoto ; Sakurai, Takayasu

  • Author_Institution
    Univ. of Tokyo, Tokyo
  • fYear
    2008
  • fDate
    21-24 Sept. 2008
  • Firstpage
    547
  • Lastpage
    550
  • Abstract
    A fine-grained body bias control to compensate both the process and design variations is proposed. A test chip was fabricated in 90nm CMOS process. The proposed global optimization scheme reduced power by 23% compared with an as-fabricated chip power and by 11% compared with the power optimized by the conventional local optimization approach. Also, the proposed global optimization scheme reduced power by 19% compared with an as-fabricated chip power within 20 test iterations with simulated annealing algorithm.
  • Keywords
    CMOS integrated circuits; circuit optimisation; CMOS process; fine-grained body biasing; global optimization scheme; power reduction; size 90 nm; CMOS process; Circuits; Clocks; Codecs; Delay estimation; Design optimization; Frequency; Process design; Semiconductor device measurement; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-2018-6
  • Electronic_ISBN
    978-1-4244-2019-3
  • Type

    conf

  • DOI
    10.1109/CICC.2008.4672143
  • Filename
    4672143
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3361230