DocumentCode
3361325
Title
Managing test, yield, quality, and cost in fabless manufacturing model
Author
Malachowsky, Chris
Author_Institution
Co-Founder, NVIDIA Fellow and Senior Vice President, Engineering and Operations
fYear
2006
fDate
22-27 Oct. 2006
Firstpage
12
Lastpage
12
Abstract
Summary form only given, as follows. Consumer products have become the main technology drivers in semiconductor manufacturing and the related market pressures have made it nearly mission impossible to achieve economically viable yields within the market window. To ensure profitability, it is imperative that all major yield loss mechanisms are identified quickly and a yield loss pareto is used to prioritize yield improvement efforts. Each yield ramp presents new challenges as the random, systematic and parametric components of the yield pareto evolve over time. Chris will discuss NVIDIA´s fabless manufacturing model with emphasis on its supply chain and how it is able to support the high velocity of NVIDIA´s business. He will address the complexities of managing multiple foundries, packaging, and test houses that all must cooperate to ensure the production of high-performance, high-quality products that are simultaneously cost effective to build, yield well, ramp quickly, and do so with the highest quality.
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2006. ITC '06. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
1-4244-0291-3
Type
conf
DOI
10.1109/TEST.2006.297731
Filename
4079409
Link To Document