It´s not what you can make - It´s what you can test

Summary form only given, as follows. This talk takes the position that the art and science of semiconductor test is on an unalterable trajectory from technology gate-keeper to technology enabler. The SIA Roadmap states emphatically "Test for yield learning (is) critically essential for fabrication process and device learning... Screening for reliability (faces) implementation challenges... and erratic, non-deterministic, and intermittent device behavior." Additional test requirements cannot change the fact that detecting active or latent defects is a rare event. To meet the challenge of yield learning, reliability screening and improving defect detection requires separating the chance occurrence from the baseline factors of process and design. New materials and processes are possible only by the transformation of production test response into test information.