DocumentCode
3361512
Title
The Design and Validation of IP for DFM/DFY Assurance
Author
Aitken, Robert
Author_Institution
ARM, Sunnyvale, CA
fYear
2006
fDate
Oct. 2006
Firstpage
1
Lastpage
7
Abstract
Design for manufacturability (DFM) is becoming increasingly important as process geometries shrink. The system-on-chip business model requires high quality, high yielding IP. This paper shows how DFM and DFY are integrated as part of IP delivery, using a set of metrics to identify and fix yield limiters without compromising power, area or performance
Keywords
design for manufacture; integrated circuit design; system-on-chip; DFM; DFY; IP design; IP validation; design for manufacturability; design for yield; system-on-chip; Design for manufacture; Geometry; Libraries; Manufacturing processes; Power system modeling; Process design; Signal processing; Silicon; System-on-a-chip; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2006. ITC '06. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
1-4244-0292-1
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2006.297742
Filename
4079420
Link To Document