Title :
Phase-locking in wireline systems: Present and future
Author_Institution :
Electr. Eng. Dept., Univ. of California, Los Angeles, CA
Abstract :
This paper describes the challenges in the design of phase-locked loops and clock and data recovery circuits as speeds approach 80-100 Gb/s. Skew and jitter issues are presented and the effect of reference phase noise, charge pump noise, reference spurs, and loop filter leakage is quantified. The phase noise performance of cascaded loops is analyzed and two new architectures are proposed.
Keywords :
jitter; phase locked loops; phase noise; synchronisation; transceivers; transmission lines; bit rate 80 Gbit/s to 100 Gbit/s; cascaded loops; charge pump noise; clock recovery circuits; data recovery circuits; jitter; loop filter leakage; phase locking; reference phase noise; reference spurs; wireline transceivers; Circuits; Clocks; Convergence; Delay; Interpolation; Jitter; Oscillators; Phase locked loops; Phase noise; Transceivers;
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
DOI :
10.1109/CICC.2008.4672162
