A tree-systolic array of DLMS adaptive filter

Author

Van, Lan-Da ; Tenqchen, Shing ; Chang, Chia-Hsun ; Feng, Wu-Shiung

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

3

fYear

1999

fDate

15-19 Mar 1999

Firstpage

1253

Abstract

In this work, we develop an optimized binary tree-level rule for the design of a systolic array structure of a delay least mean square (DLMS) adaptive filter. Using the developed method, a higher convergence rate can be obtained without sacrificing the properties of the systolic array structure. Also, based on the optimized tree rule, the user can easily design any even-number tap adaptive system with minimum delay and high regularity under the constraints of maximum driving and the total number of taps

Keywords

VLSI; adaptive filters; delay filters; least mean squares methods; systolic arrays; DLMS adaptive filter; VLSI design; convergence rate; delay least mean square adaptive filter; even-number tap adaptive system; optimized binary tree-level rule; systolic array structure; tree-systolic array; Adaptive arrays; Adaptive equalizers; Adaptive filters; Convergence; Delay; Design optimization; Filtering algorithms; Least squares approximation; System identification; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1999. Proceedings., 1999 IEEE International Conference on

Conference_Location

Phoenix, AZ

ISSN

1520-6149

Print_ISBN

0-7803-5041-3

Type

conf

DOI

10.1109/ICASSP.1999.756206

Filename

756206