Are Design for Debug (DFD) Features that are Put in Reuse Cores Sufficient for Silicon Debug? - position statement

What types of debug capability can currently be found in cores? The first thing that comes to mind is scan. Though scan was originally implemented in order to get high fault coverage, it can also be used for debug. For instance, if there is an asynchronous switch from functional mode to scan mode, a functional test can be run, stopped and then the data in every scanned register can be shifted out to help determine the failure area. Scan can also help in determining critical frequency areas of the design. Delay patterns can be created and if they fail, the failing register or registers can be easily determined. There may need to be infrastructure that allows the delay pattern to be implemented in such a way that power and vdd droop during test can be manipulated to be close to what the power and IR drop is during functional mode. There are many other fault models for scan (e.g.stuck-at, bridging) that can be utilized and if the pattern fails, the failure can easily be traced