Title :
SOC and Multicore Debug: Are Design for Debug (DFD) Features that Are Put in Re-use Cores Sufficient for Silicon Debug?
Author_Institution :
Intel Corp., Santa Clara, CA
Abstract :
While reuseable cores and SOC components are delivered along with a "complete" test suite to ensure good functional test coverage, this is inadequate for silicon debug
Keywords :
design for testability; system-on-chip; design for debug; functional testing; multicore chips; reuseable cores; silicon debug; system-on-chip; Automatic testing; Circuit testing; Design for disassembly; Design for testability; Educational institutions; Logic arrays; Logic circuits; Logic testing; Multicore processing; Silicon;
Conference_Titel :
Test Conference, 2006. ITC '06. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
1-4244-0292-1
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2006.297761
