Abstract :
Traditionally, developers of multi-core chips have relied upon system-level techniques such as boundary scan and external instrumentation to access internal signals during silicon debug. The system-on-a-chip (SoC) nature of the cell processor makes it more difficult to rely on these techniques, as the system bus is internal to the chip, and only a limited number of pins are accessible. The cell development team was thus presented with the challenge of designing a sufficient built-in facility that could provide visibility to critical nodes within cell´s multiple partitions. The team answered this challenge with the design of cell´s centralized trace logic analyzer. The cell trace logic analyzer is a powerful built-in tool that allows for debug and analysis of processor components by providing a window to internal signals. Its main components are the debug bus, match logic, state control logic, and trace array. The centralized approach allows for a high degree of user programmability and flexibility that would not otherwise be feasible under typical design constraints
Keywords :
built-in self test; design for testability; logic analysers; logic testing; system-on-chip; boundary scan; cell processor; debug bus; design for debug; match logic; multicore chips; silicon debug; state control logic; system-on-chip; trace array; trace logic analyzer; user programmability; Design for disassembly; Instruments; Logic arrays; Logic design; Pins; Signal analysis; Signal processing; Silicon; System buses; System-on-a-chip;
