A method using circuit/substrate macro modeling to analyze substrate noise in a 3.2-GHz 350M-transistor microprocessor

Substrate noise analysis has become increasingly important in recent LSI design. This is because substrate noise, which affects PLLs, causes jitter that results in timing error. Conventional analysis techniques of substrate noise are, however, impractical for large-scale designs that have hundreds of millions of transistors because the computational complexity is too huge. To solve this problem, we have developed a fast substrate noise analysis technique for large-scale designs, one in which a chip is divided into multiple domains by using current density variation and the circuits of each domain are reduced into a macro model. Using this technique, we have designed a microprocessor chip for use in the supercomputer SX-9 (die size: 20 mm times 21 mm, frequency: 3.2 GHz, transistor count: 350 M). Computation time with this design is five times shorter than [2] that with a 1/3000 scale design using a conventional technique, while resulting discrepancy with measured period jitter is less than 15%.