Role of test in yield learning for 65nm and beyond

A robust design for test (DFT) architecture and the ability to detect small delay defects are not enough to meet all of today\´s customer requirements. Customers must also achieve expedient yield ramp especially in highly volatile and cost sensitive markets. This requires a stateof- the-art Volume Yield Diagnostics flow with a highly accurate diagnostic engine and a deep integration extending into the design domain. With the advent of nanometer technologies, design yields are more often limited by context sensitive design "features" (wire length, contact closure distance, via formation etc.) than by random particle defects. In order to bridge the gap between feature-limited and defect-limited yield loss, diagnostics based yield ramp and yield learning technologies must be deeply integrated into the design layout to identify exact locations on the die where yield loss is the greatest and more importantly, provide a closed loop system to enhance DFM models, library design and design rules for higher yielding designs. This situation at 65 and 45nm is moving the EDA industry from that of a supplier of point tools to the role of a partner proactively anticipating and delivering on customers?? needs, it is becoming increasingly clear that our customers expect systematic delivery of Testability solutions from system to silicon.