Static power optimization of a Full-Adder under Front-End of Line systematic variations

Process variation as a major concern in the current and future generations of CMOS circuits manufacturing has imposed a great deal of effort in design process. Basically, process variations are generally divided in two main categories: random variations and systematic variations. Therefore, physical designers of integrated circuits (ICs) have to take into account the effects of random and systematic process variations in the design process. As the critical dimension (CD) of transistors scale down, the effects of Front-End of Line (FEOL) systematic variations have been proved to be a great contributor of performance variability of ICs. Because of Across Chip Line-Width (ACLV) variation during lithography process, the channel length of transistor is subject to remarkable variations. As a result, the performance of IC becomes highly sensitive to these variations. In this paper we propose a leakage-aware optimization methodology which improves the performance of circuit in terms of standby static power and power delay product (PDP). We apply this methodology on a conventional ripple-carry full-adder as a basic block in VLSI circuits and systems for verification purposes. Besides, this method effectively improves the static power yield by almost 14% in average.