FPGA implementation of Rijndael algorithm using reduced residue of prime numbers

This paper describes the field programmable gate array (FPGA) implementation of Rijndael algorithm based on a novel design of S-box built using reduced residue of prime numbers. The objective is to present an efficient hardware implementation of Rijndael using very high speed integrated circuit hardware description language (VHDL). The novel S-box look up table (LUT) entries forms a set of reduced residue of prime number, which forms a mathematical field. The S-box with reduced residue of prime number adds more confusion to the entire process of Rijndael and makes it more complex and immune to algebraic attacks. The target hardware used in this paper is state-of-the-art Xilinx Virtex-5 XC5VLX50 FPGA. The proposed design achieves a throughput of 3.09 Gbps using only 1745 slices.