DocumentCode :
3362548
Title :
An all-digital direct digital synthesizer fully implemented on FPGA
Author :
Omran, Hesham ; Sharaf, Khaled ; Ibrahim, Magdy
Author_Institution :
Electron. & Commun. Eng. Dept., Ain Shams Univ., Cairo, Egypt
fYear :
2009
fDate :
15-17 Nov. 2009
Firstpage :
1
Lastpage :
6
Abstract :
In this paper an all-digital pulse output direct digital synthesizer (DDS) is described. The synthesizer is fully implemented on FPGA and does not require any external analog components. Selective over-sampling and tapped delay line are used to reduce jitter and improve spectral performance. Selective over-sampling relaxes the requirements on the delay line with a minor effect on power consumption and circuit complexity. The delay line is implemented using the FPGA digital clock manager (DCM). The synthesizer generates clock signals with maximum output frequency up to fclk. It achieves sub-Hz resolution and sub-¿s switching time. Experimental measurements validate system operation with spurious free dynamic range (SFDR) greater than 40 dB.
Keywords :
clocks; direct digital synthesis; field programmable gate arrays; frequency synthesizers; power consumption; FPGA digital clock manager; all-digital pulse output direct digital synthesizer; circuit complexity; clock signals; delay line; power consumption; selective over-sampling; spectral performance; spurious free dynamic range; Clocks; Complexity theory; Delay lines; Energy consumption; Field programmable gate arrays; Frequency synthesizers; Jitter; Power system management; Signal generators; Signal resolution; Direct digital synthesizer (DDS); field-programmable gate array (FPGA); over-sampling; spurious free dynamic range (SFDR);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Test Workshop (IDT), 2009 4th International
Conference_Location :
Riyadh
Print_ISBN :
978-1-4244-5748-9
Type :
conf
DOI :
10.1109/IDT.2009.5404133
Filename :
5404133
Link To Document :
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