• DocumentCode
    3362596
  • Title

    The design of a 14 GHz I/Q ring oscillator in 0.18 μm CMOS

  • Author

    Eken, Yalcin A. ; Uyemura, John P.

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
  • Volume
    4
  • fYear
    2004
  • fDate
    23-26 May 2004
  • Abstract
    This paper presents the design of a 14 GHz ring VCO with in-phase/quadrature (I/Q) outputs in a standard 0.18 μm CMOS process. A four stage multiple-pass ring oscillator is coupled with frequency doublers for obtaining high frequencies. The VCO core uses delay stages with cross-coupled FETs to increase the switching speed and to improve the noise parameters. The proposed design has a tuning range of 8.5 to 14 GHz (49%), and exhibits -95.35 dBc/Hz phase noise (@ 1 MHz) at a center frequency of 12.7 GHz while consuming 146 mW from a 1.8 V power supply. The results suggest that it is not always necessary to resort to integrated LC networks for 10+ GHz VCO/CCO modules but that cost and area effective ring designs may suffice.
  • Keywords
    CMOS integrated circuits; circuit tuning; frequency multipliers; integrated circuit design; phase noise; voltage-controlled oscillators; 0.18 micron; 1.8 V; 146 mW; 8.5 to 14 GHz; CMOS process; circuit tuning range; cross coupled FET; effective ring design; frequency doubler; inphase-quadrature ring oscillator; integrated LC network; multiple pass ring oscillator; noise parameter; phase noise; switching speed; voltage controlled oscillator design; CMOS process; Costs; Delay; FETs; Frequency; Phase noise; Power supplies; Ring oscillators; Tuning; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
  • Print_ISBN
    0-7803-8251-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.2004.1328958
  • Filename
    1328958