Design of LNA at 2.4 GHz using 0.25 /spl mu/m technology

Author

Xiaomin Yang ; Wu, T. ; McMacken, John

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Central Florida Univ., Orlando, FL, USA

fYear

2001

fDate

14-14 Sept. 2001

Firstpage

12

Lastpage

17

Abstract

Two 2.4 GHz CMOS low noise amplifiers have been designed in a 0.25 /spl mu/m CMOS process. One is single-ended, and the other is differential. Both are fully integrated, without off-chip components. The design procedure and simulation results are presented in this paper. With a 3.3 V supply, the LNAs achieve power gains of 15 dB and 20 dB, noise figures of 2.2 dB and 2.4 dB, and third-order input intercept points (IIP3) of 1.3 dBm and 3.4 dBm. The power dissipations are 7.2 mW and 4.8 mW respectively. In the differential LNA design, a smaller die area is achieved using an LC tank to replace a large inductor.

Keywords

CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; circuit simulation; differential amplifiers; integrated circuit design; integrated circuit noise; 0.25 micron; 15 dB; 2.2 dB; 2.4 GHz; 2.4 dB; 20 dB; 3.3 V; 4.8 mW; 7.2 mW; CMOS low noise amplifiers; CMOS process; CMOS technology; LC tank; LNA design; design procedure; die area; differential LNA; differential LNA design; fully integrated LNA design; large inductor; noise figure; off-chip components; power dissipation; power gain; simulation; single-ended LNA; supply voltage; third-order input intercept points; CMOS process; CMOS technology; Gain; Inductors; Low-noise amplifiers; Noise figure; Power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems, 2001. Digest of Papers. 2001 Topical Meeting on

Conference_Location

Ann Arbor, MI, USA

Print_ISBN

0-7803-7129-1

Type

conf

DOI

10.1109/SMIC.2001.942333

Filename

942333