DocumentCode :
3362738
Title :
An s-domain based framework for accurate and efficient static waveform analysis
Author :
Shebaita, Ahmed ; Petranovic, Dusan ; Ismail, Yehea
fYear :
2009
fDate :
15-17 Nov. 2009
Firstpage :
1
Lastpage :
6
Abstract :
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The novel methodology uses the traditional cell library table structure with one modification, instead of filling the cell library tables with the 50% delay and slew of the gate output signal, the cell library tables are filled with the gate output signal moments. This approach eliminates the error due to the ramp approximation at the gate output which is based only on the 50% delay and slew. Simple convolution of the gate output moments by the interconnect moments yields the signal moments at the stage output. The parameters of the gate input signal, which are used for the table access of the successive stage, are directly computed from the predecessor stage output moments using closed form expressions. Thus, the interconnects and the gates are uniformly treated in a moment-based homogeneous framework. The novel approach inherits the classical cell library tables approach efficiency with even reduced computation complexities. As compared to the classical cell library table approach, the proposed approach accounts for the increasingly nonlinear waveform shapes and provides accuracy and flexibility in the path performance calculations. Increasing the accuracy in the novel approach is made flexible by simply using more moments. To illustrate the concept and prove its merits, multiple examples are presented with 2-3 moments which maintain accuracy within 1-3% versus 10-20% for the classical cell library table approach as compared to SPICE.
Keywords :
SPICE; integrated circuit interconnections; logic analysers; logic gates; waveform analysis; cell library tables approach efficiency; static timing analysis; static waveform analysis; Capacitance; Density functional theory; Filling; Graphics; Integrated circuit interconnections; Inverters; Libraries; Nanoelectronics; Propagation delay; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Test Workshop (IDT), 2009 4th International
Conference_Location :
Riyadh
Print_ISBN :
978-1-4244-5748-9
Type :
conf
DOI :
10.1109/IDT.2009.5404146
Filename :
5404146
Link To Document :
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