Scaleable check node centric architecture for LDPC decoder

Low density parity check codes are a popular class of linear block codes for forward error correction in communication channels. Recent years have seen a lot of work towards the development of decoding architectures for these codes. The architectures range from completely parallel to completely serial. While the parallel architectures have a high throughput, they have a large hardware resource requirement. On the other hand, although the serial architectures are very efficient in terms of hardware requirement, they suffer from low throughput. This paper presents a novel scalable check node centric architecture with a 1.5 Gbps throughput. The throughput may be further increased by using more readily scalable data-paths which have a individual throughput of 0.5 Gbps.