A Scan Flip-Flop for Low-Power Scan Operation

Power dissipation in digital systems may be significantly high during scan testing where a large portion of power is consumed in the combinational part. This paper presents a new scan Flip-Flop design to eliminate test power consumption in the combinational block during scan shifting by masking signal transitions at the combinational logic inputs. The new scheme achieves the same power reduction in the scan mode of operation as earlier approaches in the open literature, while it presents better propagation times, in the normal mode, and significantly lower silicon area overhead.