Modeling and characterization of Cu wire bonding process on silicon chip with 45nm node and Cu/low-k structures

Due to the rapid increase of Au price in recent years, there is an emerging trend to use Cu to replace Au in wire bonding because Cu wire not only has lower cost but also has superior electrical, mechanical and thermal properties. However, Cu ball is much harder than Au ball so that there are several challenges for applying Cu wire bond such as excessive deformation of the Al bond pad and dielectric layer crack under the bond pads, especially for low-k structures. In this study, the stress sensors were designed in the test chips and used to measure under pad stress in real-time. Dynamic finite element modeling methodology was developed for wire bonding process and validated by stress measurement. Parametric studies were conducted using numerical modeling to find ways to reduce Al deformation and stresses by adjusting parameters.