Comparison of VLSI architectures for a WLAN OFDM transmitter with interpolation filters

This paper introduces two efficient computational techniques for Orthogonal Frequency Division Multiplexing (OFDM) based transmitter design with interpolation filters and discusses the corresponding VLSI architecture issues. The proposed technique is demonstrated by detailing the implementation of a 64-point, radix-2⁴ SDF FFT in combination with digital interpolation filters. By exploiting the redundancy into the cyclic prefix part of the OFDM symbol, the computational load of the transmitter is reduced by approximately 20% for the IEEE 802.11 WLAN standard. The first technique outperforms the second one regarding the number of operations, while the second one is more appealing for applications where required area is an issue.