DocumentCode
3363011
Title
CMOS programmable divider for Zigbee frequency synthesizer
Author
Ismail, Nesreen Mahmoud Hammam ; Othman, Masuri
Author_Institution
Inst. of MicroEngineering & Nanoelectron., Univ. Kebangsaan Malaysia (UKM), Bangi, Malaysia
fYear
2009
fDate
15-17 Nov. 2009
Firstpage
1
Lastpage
3
Abstract
This paper presents a 4 bit integer N CMOS programmable frequency divider with high speed and low power consumption. It is based on a dual-modulus prescaler, and programmable asynchronous and synchronous dividers. It works up to 3.4 GHz frequency clock. It is tested in PLL for 2.4 GHz band Zigbee standard. All results are taken from simulating extracted layout. It is implemented using Silterra 0.18 CMOS process, voltage supply 1.8 V, and consumes 0.7 mW.
Keywords
CMOS integrated circuits; frequency dividers; frequency synthesizers; integrated circuit testing; low-power electronics; phase locked loops; programmable circuits; CMOS programmable divider; PLL; Zigbee frequency synthesizer; Zigbee standard; dual-modulus prescaler; frequency clock; low power consumption; voltage 1.8 V; Frequency synthesizers; ZigBee; Integer N Divider; Phase Locked Loop; Programmable Divider; Zigbee;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Test Workshop (IDT), 2009 4th International
Conference_Location
Riyadh
Print_ISBN
978-1-4244-5748-9
Type
conf
DOI
10.1109/IDT.2009.5404161
Filename
5404161
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