Title :
3.5-Gb/s extended frequency range wave-pipeline PRBS Generator in 0.18-μm CMOS
Author :
Sasaki, Masahiro ; Ikeda, Makoto ; Asada, Kunihiro
Author_Institution :
VLSI Design and Education Center (VDEC), Univ. of Tokyo, Tokyo
Abstract :
A 3.57-Gb/s, low-power, 2 31-1 output length, extended frequency range Pseudo Random Binary Sequence (PRBS) generator with an improved wave-pipeline technique is presented. The previous wave-pipeline technique bypasses the portion of feedback loop, and thereby relaxes the timing restriction of the critical path up to two shifting clock periods. While the generator operates at the 48% higher frequency (4- Gb/s) than the conventional one (2.7-Gb/s), there is a low operating frequency limit. Therefore, we propose an improved wave-pipeline technique which enables to operate in the extended frequency range from 0 ~ 1.85-Gb/s and 2.56 ~ 3.57- Gb/s by function of detecting a sequence error and switching from the normal mode to the wave-pipeline mode. Thus, the generator has achieved the 32% higher maximum operating frequency (3.57-Gb/s) than the conventional one.
Keywords :
CMOS integrated circuits; binary sequences; feedback; random sequences; CMOS; bit rate 0 Gbit/s to 1.85 Gbit/s; bit rate 2.56 Gbit/s to 3.57 Gbit/s; bit rate 4 Gbit/s; efficiency 32 percent; efficiency 48 percent; feedback loop; pseudo random binary sequence generator; sequence error; size 0.18 mum; wave-pipeline PRBS Generator; Binary sequences; Bit error rate; Built-in self-test; CMOS logic circuits; CMOS technology; Energy consumption; Frequency; Power generation; Power supplies; Testing;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4511044
