Re-Using Clock Management Unit to implement Power Gating and Retention for Leakage Reduction at the 65-nm Technology Node

Author

Royannez, P. ; Jumel, F. ; Mair, H. ; Scott, D. ; Rachidi, A. Er ; Lagerquist, R. ; Chau, M. ; Gururajarao, S. ; Thiruvengadam, S. ; Clinton, M. ; Menezes, V. ; Hollingsworth, R. ; Vaccani, J. ; Piacibello, F. ; Culp, N. ; Rosal, J. ; Ball, M. ; Ben-Amar,

Author_Institution

Texas Instrum. Inc., Villeneuve Loubet

fYear

2007

fDate

May 30 2007-June 1 2007

Firstpage

1

Lastpage

2

Abstract

Leakage power management, wireless SoC In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-uA range and overall 1200X leakage reduction including process, circuit and system optimization.

Keywords

modems; system-on-chip; clock management unit; digital base band modem; leakage management system; leakage reduction; power gating; system optimization; Clocks; Control systems; Energy management; Leakage current; Modems; Power system management; Random access memory; Switches; Technology management; Voltage; Leakage power management; wireless SoC;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

1-4244-0757-5

Electronic_ISBN

1-4244-0757-5

Type

conf

DOI

10.1109/ICICDT.2007.4299538

Filename

4299538