A linearization technique for RF low noise amplifier

Author

Xin, Chunyu ; Sánchez-Sinencio, Edgar

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

Volume

4

fYear

2004

fDate

23-26 May 2004

Abstract

A LNA linearization technique derived from multi-gated configuration using bipolar transistors in CMOS technology is proposed. A bipolar transistor is used to replace the auxiliary MOS transistor to achieve higher operational speed. Both single-ended and differential applications are investigated. Simulation shows that this method is competitive with already reported low noise amplifiers. For 3 GHz of frequency operation, the single-ended structure achieves +15 dBm IIP3 with 8.9 mW power consumption, and the differential architecture can achieve +14 dBm IIP3 with 21 mW power consumption.

Keywords

BiCMOS integrated circuits; differential amplifiers; high-speed integrated circuits; integrated circuit modelling; integrated circuit noise; linearisation techniques; radiofrequency amplifiers; 21 mW; 3 GHz; 8.9 mW; CMOS technology; LNA linearization technique; MOS transistor; RF low noise amplifier; bipolar transistors; differential applications; frequency operation; multigated configuration; power consumption; single-ended applications; single-ended structure; third order input intercept point; Bipolar transistors; CMOS technology; Energy consumption; Linearity; Linearization techniques; Low-noise amplifiers; MOSFETs; Radio frequency; Radiofrequency amplifiers; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329003

Filename

1329003