A fast and exact cell matching method for MUX-based FPGA technology mapping

Presents a new cell matching method which could be effectively used for MUX-based FPGA technology mapping. In this method, a well-organized cell library of a manageable size is constructed for each target architecture a priori, and cell matchings are performed by searching the corresponding entry in the library using integer comparison operations. Experimental results for some MCNC benchmarks show that our approach indeed reduces the computation time significantly, while preserving the exact cell matching