A fast-lock DLL with power-on reset circuit

This paper describes a fast-lock delay-lock loop (DLL) with power-on reset (POR) circuit. The POR circuit and coarse tune (CT) circuit are proposed to overcome the problems of the false locking associated with conventional DLL´s and offer the faster locking time. Moreover, the proposed VCDL can reduce dynamic switching power dissipation and noise. The chip is fabricated in a 0.35 μm CMOS process. From the measurement results, the DLL can operate correctly from 100 to 190 MHz and generate equally spaced eight-phase clocks. When the input clock frequency is 100 MHz, the measured output clock peak-to-peak jitter and rms jitter are 56 ps and 12.44 ps, respectively. And when the input clock frequency is 190 MHz, the measured output clock peak-to-peak jitter and rms jitter are 46 ps and 8.463 ps, respectively. Besides, the maximum lock time is 43 clock cycles at 150 MHz.