A simple limit cycle suppression scheme for hysteresis current controlled PWM VSI with consideration of switching delay time

A novel suppression scheme for switching known as the limit cycle in a hysteresis current controller is presented. The proposed method is based on the concept of superimposing a common offset signal, which has both proper amplitude and pattern, on three-phase current references, and does not need any additional circuit. It is verified that the switching interference occurs more easily and directly depends on the period of the delay time. Moreover, the switching delay time also significantly influences the effect of limit cycle suppressions. It is seen that with the proposed method the switching interference is greatly suppressed even if the switching delay time exists. Simulations and experiments are performed to verify the effectiveness of the proposed method, and some results are presented