Title :
A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications
Author :
Mak, Pui-In ; U, Seng-Pan ; Martins, R.P.
Author_Institution :
Analog & Mixed-Signal VLSI Lab., Univ. of Macau, Macao, China
Abstract :
This paper presents a low-IF/zero-IF reconfigurable receiver for multistandard applications based on a two-step channel selection (2-SCS) technique. Such technique is mainly implemented by a reconfigurable sampling scheme, which can perform either programmable Analog-Double Quadrature Sampling (A-DQS) or Analog-Baseband Sampling (A-BS) to, first, relax the front-end PLL-frequency synthesizer (PLL-FS) locking time and phase noise requirements; and, second, allow a low-IF architecture to be transformable to zero-IF with small overheads. In this way, the receiver can operate in low-IF mode for narrowband standards avoiding 1/f noise and DC offset, and alternatively, for wideband standards, it can be reconfigured seamlessly in zero-IF mode to minimize image interference. The operating principles, design considerations and circuit implementation of such schemes for multistandard applications, including Bluetooth, HomeRF and IEEE 802.11FH, demonstrate the flexibility of such topology.
Keywords :
1/f noise; Bluetooth; analogue-digital conversion; frequency synthesizers; phase locked loops; phase noise; radio receivers; telecommunication channels; 1/f noise; Bluetooth; HomeRF; PLL-frequency synthesizer; analog baseband sampling; analog double quadrature sampling; circuit implementation; image interference; low IF-zero IF reconfigurable receiver; phase noise; reconfigurable sampling scheme; two step channel selection technique; Bluetooth; Circuit noise; Circuit topology; Flexible printed circuits; Interference; Narrowband; Phase noise; Sampling methods; Synthesizers; Wideband;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1329029