Title :
A Pipelined 12-bit Analog-to-Digital Converter with Continuous On-Chip Digital Correction
Author :
Ekekwe, Ndubuisi ; Ekenedu, Chinyeaka
Author_Institution :
Johns Hopkins Univ., Baltimore
Abstract :
A 12-bit 43MHz switched capacitor pipelined analog-to-digital converter was implemented in a 0.5¿m 2P3M CMOS process based on 1.5-bit/stage architecture. The design features an on-chip continuous digital correction and a fully differential signal path circuitry that minimizes noise and relaxes comparator offset requirements. The design is a fully monolithic design that achieved an integral non-linearity of ± 0.7 LSB and differential non-linearity of ±0.8 LSB with power dissipation of 94mW.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; integrated circuit design; logic design; pipeline processing; switched capacitor networks; system-on-chip; 2P3M CMOS process; comparator offset; continuous on-chip digital correction; differential signal path circuitry; frequency 43 MHz; monolithic design; pipelined analog-to-digital converter; power 94 mW; size 0.5 mum; switched capacitor; Analog-digital conversion; CMOS process; Circuits; Clocks; Computer architecture; Instruments; Pipelines; Signal design; Signal processing; Signal resolution;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4511080
