Title :
Design Asynchronous Circuits for Soft Error Tolerance
Author :
Kuang, Weidong ; Xiao, Enjun ; Ibarra, Casto Manuel ; Zhao, Peiyi
Author_Institution :
Univ. of Texas-Pan American, Edinburg
fDate :
May 30 2007-June 1 2007
Abstract :
This paper presents a quasi delay insensitive (QDI) asynchronous circuit design paradigm -modified Null Convention Logic (NCL), for high single event upset (SEU) tolerance We investigate the behavior of the QDI circuit in the presence of SEUs, and propose a framework to evaluate the SEU sensitivity of the circuit. The modified NCL circuit can eliminate all SEUs in computational blocks if these SEUs occur when the computational blocks are in steady sates. Finally we present a case study of a two-bit adder.
Keywords :
adders; asynchronous circuits; delay circuits; logic design; tolerance analysis; NCL; QDI; asynchronous circuit design; computational blocks; modified null convention logic; quasi delay insensitive circuit; single event upset tolerance; soft error tolerance; two-bit adder; Asynchronous circuits; Circuit faults; Delay; Hysteresis; Logic circuits; Pipelines; Registers; Single event upset; Timing; Very large scale integration;
Conference_Titel :
Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
1-4244-0757-5
Electronic_ISBN :
1-4244-0757-5
DOI :
10.1109/ICICDT.2007.4299578
