2Mb SPRAM Design: Bi-Directional Current Write and Parallelizing-Direction Current Read Schemes Based on Spin-Transfer Torque Switching

Author

Takemura, R. ; Kawahara, T. ; Miura, K. ; Hayakawa, J. ; Ikeda, S. ; Lee, Y.M. ; Sasaki, R. ; Goto, Y. ; Ito, K. ; Meguro, T. ; Matsukura, F. ; Takahashi, H. ; Matsuoka, H. ; Ohno, H.

fYear

2007

fDate

May 30 2007-June 1 2007

Firstpage

1

Lastpage

4

Abstract

A 1.8 V 2-Mb SPRAM (SPin-transfer torque RAM) chip using 0.2-mum logic process with MgO tunneling barrier cell demonstrates the circuit technologies for potential low power non-volatile RAM, or universal memory. This chip features: an array scheme with bit-by-bit bi-directional current write to achieve proper spin-transfer torque writing of 100-ns, and parallelizing-direction current reading with low voltage bit-line that leads to 40-ns access time.

Keywords

random-access storage; switching; tunnelling; SPRAM design; SPin-transfer torque RAM chip; bi-directional current write scheme; logic process; nonvolatile RAM; parallelizing-direction current read scheme; spin-transfer torque; spin-transfer torque switching; tunneling; Bidirectional control; Driver circuits; Laboratories; Latches; Nonvolatile memory; Random access memory; Read-write memory; Switches; Torque; Writing; Spin-transfer torque; TMR; low power RAM; nonvolatile RAM; universal RAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

1-4244-0757-5

Electronic_ISBN

1-4244-0757-5

Type

conf

DOI

10.1109/ICICDT.2007.4299581

Filename

4299581