Title :
No-Handshake Asynchronous Survivor Memory Unit for a Viterbi Decoder
Author :
Shao, Wei ; Brackenbury, Linda
Author_Institution :
Univ. of Manchester, Oxford
Abstract :
The Survivor Memory Unit (SMU) is a vital part of a Viterbi decoder design. So far, classical implementations of SMU employ the register exchange or the trace back approaches. In the conventional trace back implementation, a read-write RAM architecture is generally adopted which requires a large size of memory. This gives the SMU design both area and power overhead. This paper presents a new no-handshake asynchronous approach to implement the trace back method. The SMU design based on this new architecture is a mixed synchronous and asynchronous circuit. Post-layout simulation results on a .18¿m process show the new architecture saves more than 84% of the power dissipated compare with a synchronised SMU design using a low power logic family and 30% compared with a handshaking asynchronous design.
Keywords :
CMOS memory circuits; Viterbi decoding; field programmable gate arrays; integrated circuit design; low-power electronics; CMOS circuitry; FPGA implementation; Viterbi decoder design; asynchronous survivor memory unit; conventional trace back implementation; handshaking asynchronous design comparison; mixed synchronous-asynchronous circuit; no-handshake asynchronous approach; size 0.18 mum; trace back logic; Algorithm design and analysis; Computer science; Convolution; Convolutional codes; Decoding; History; Random access memory; Read-write memory; Registers; Viterbi algorithm;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4511095
