DocumentCode
3364212
Title
Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs
Author
Itoh, Kiyoo ; Takemura, Riichiro
Author_Institution
Hitachi Ltd., Tokyo
fYear
2007
fDate
11-14 Dec. 2007
Firstpage
739
Lastpage
742
Abstract
The minimum operating voltage (Vmin ) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT ) of MOSFETs. The Vmin , however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k metal gates) that can reduce VT variations.
Keywords
CMOS memory circuits; DRAM chips; MOSFET; SRAM chips; large scale integration; logic gates; nanoelectronics; DRAM sense amplifiers; MOSFET; SRAM cells; logic gates; low-voltage limitations; memory-rich nano-scale CMOS LSI; minimum operating voltage; threshold voltage; CMOS logic circuits; Combinational circuits; Degradation; Laboratories; Large scale integration; Logic devices; Logic gates; MOSFETs; Random access memory; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location
Marrakech
Print_ISBN
978-1-4244-1377-5
Electronic_ISBN
978-1-4244-1378-2
Type
conf
DOI
10.1109/ICECS.2007.4511097
Filename
4511097
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