Optimal Design Methodology for High-Order Continuous-Time Wideband Delta-Sigma Converters

A systematic design methodology for high-order continuous-time wideband Delta-Sigma modulators is proposed. This method provides a direct way for determining the coefficients of the modulator. Trade-offs between the choice of the coefficients and the power consumption is analyzed. The method is illustrated for a 4^th-order 4-bit modulator with OSR of 8, while 20 MHz signal bandwidth and 12 bit resolution is achieved. The required GBW of the first integrator is less than 1.5 times the sampling frequency, which reduces the overall power consumption.