Title :
Sizing low-voltage CMOS analog circuits
Author_Institution :
Univ. Catholique de Louvain, Louvain-la-Neuve
Abstract :
A simple yet accurate MOS model intended for sizing CMOS analog circuits by means of the gm/ID methodology is proposed. The E.K.V.1 model is a good candidate but applies only to long channel transistors. Making the parameters functions of the source and drain voltage extends the model to short channel devices.
Keywords :
CMOS analogue integrated circuits; low-power electronics; EKV 1 model; MOS model; low-voltage CMOS analog circuit; Analog circuits; CMOS analog integrated circuits; Degradation; Electronic mail; MOSFETs; Parasitic capacitance; Performance gain; Semiconductor device modeling; Threshold voltage; Transconductance;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4511100
