Interconnect technologies for system-in-package integration

Heterogeneous system integration is a powerful approach to combine chips and components from different technologies into highly functional products with small form factors. Interconnect technologies are key to any such integration concepts. Because of the increasing challenge of cost efficiency, appropriate system-in-package (SiP) platform technologies are required that offer flexible use based upon processing options and modular production capabilities. Today, typical interconnects in a SiP toolbox are new technologies like redistribution layers (RDLs), 3D thru-silicon vias (TSVs) and 3D thru-encapsulant vias (TEVs) in addition to innovative variations of flip-chip bonding, wire bonding, and several options for die attach. Such interconnects enable the 3D integration of stacked or embedded chips and other components like passives, shielding or antennas. Scaling trends in component density (Moore´s law) and computing efficiency (Koomey´s law) allow circuit miniaturization and increased functionality of logic ICs, but also drive the necessary number of external input/output pins of the packaged system (Rent´s rule). Often, this results in small ball pitch dimensions enabled by usage of high-density BGA substrates or fan-out packages with adequate redistribution layers. Moreover, increasing power densities demand efficient thermal coupling between chip, package, and board. Heat dissipation has become an important topic for both logic and power semiconductors systems. In this paper, main highperformance interconnect technologies are discussed. In a first example, we discuss the interconnect capabilities of the very thin (~ 0.3 mm) TSLP package platform meanwhile in mass production for various designs. We especially highlight the embedded Wafer Level Ball Grid Array (eWLB) technology, an example for a highly flexible system integration platform. Similarly, the new Blade technology of Infineon offers important advantages for power semiconductor systems by means of lo- parasitic interconnects and redistribution capability.