Title :
The design of a differential CMOS charge pump for high performance phase-locked loops
Author :
Terlemez, Bortecene ; Uyemura, John P.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
The design methodology and the test results of a low-voltage differential charge pump structure for phase-locked loop (PLL) applications are presented. The structure is composed of two charge/discharge blocks, a replica bias circuit, and a sampled data common-mode feedback (CMFB) block that adjusts the pump-up current for symmetrical differential outputs and a wider output voltage range. A prototype is fabricated using a 0.18 μm n-well CMOS technology to test the charge pump in a high performance PLL, running internally at 2.5 GHz with -123 dBc/Hz phase noise at 1 MHz frequency offset.
Keywords :
CMOS integrated circuits; differential amplifiers; feedback amplifiers; high-speed integrated circuits; integrated circuit layout; integrated circuit noise; low-power electronics; phase detectors; phase locked loops; sampled data circuits; 0.18 micron; 2.5 GHz; CMOS technology; PLL applications; charge-discharge blocks; high performance phase-locked loops; low voltage differential CMOS charge pump; phase noise; prototype; pump-up current; replica bias circuit; sampled data common-mode feedback block; symmetrical differential outputs; wider output voltage range; CMOS technology; Charge pumps; Circuit testing; Design methodology; Feedback circuits; Output feedback; Phase locked loops; Phase noise; Prototypes; Voltage;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1329065
