Optimization for temporary bonding process in PECVD passivated micro-bumping technology

One of the key processes of 3-D IC technology is the implementation of a temporary bonding solution that gives the ability to handle and process thinned Si wafers. Figure 1 depicts thin composite wafers going through a typical process from bare wafer through micro-bumping. The thin composite wafers are processed (Figure 1, steps 7 to 11) sequentially including PECVD, sputtering, patterning, electro-plating, photoresist (PR) stripping, and reflow. In general, the dielectric quality and surface conformity of most plasma-deposited insulators increases significantly as the temperature increases from 200°C to 300°C [1]. Hence, the process of PECVD includes higher temperatures (>200°C) and longer times (~10 minutes) compared with other processes. Chipping or cracking may occur at the wafer edge after the PECVD process [2]. Some dishing as large as a chip size (5 mm × 5 mm) can also randomly occur at the wafer surface, as shown in Figure 2 [3], presumably caused by outgassing from the adhesive layer [2]. Therefore, it is critical to account for PECVD when designing the temporary bonding process. Due to the long high-temperature thermal treatment in the PECVD process, bonding materials play a critical role. The work described here utilized WaferBOND® advanced bonding material and ZoneBOND® technology from Brewer Science, Inc. The impact of the bonding materials with different thermal stability, provided by Brewer Science, are studied in this paper. Glass total thickness variation (TTV) and flatness impacts the overall performance of temporary bonding technology [4]. Also, deposition of certain coatings can impact the flatness (warp/bow) of high-aspect-ratio wafers. Finally, mismatch of the coefficient of thermal expansion (CTE) of the various components of a bonded stack will also affect the overall flatness as a function of process temperature. For these reasons, a study was conducted to better understand the impact of w- rpage and CTE of the glass carrier wafer, as well as the impact of coating-induced warpage on the performance of a temporary bonding/debonding process. An L9 Taguchi experiment method was used with split condition design to understand the parameters of this study. A PECVD process at 250°C with different thickness was performed in the Electronics and Optoelectronics Lab (EOL) within the Industrial Technology Research Institute (ITRI) to coat the Si wafers. Corning® Semiconductor Glass Wafers and simulated silicon (Si) wafers were carefully treated and coated with ZoneBOND® advanced materials and WaferBOND® bonding material. After bonding, simulated processes (e.g., silicon nitride coating) were performed. At each step, Corning´s FlatMaster® MSP 300 tool was used to collect thickness variation and warpage data to evaluate the performance of the temporary bonding process.