Title :
A comparative study of LOCOS-type isolations for 256 Mbit DRAM
Author :
Chen, I.C. ; Rodder, M. ; Hwang, J.-M.
Author_Institution :
Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA
fDate :
31 May-2 Jun 1995
Abstract :
Three LOCOS-type isolations, viz. modified Scaled LOCOS (MSL), Sidewall Sealed MSL (SSMSL), and Recessed SSMSL (RSSMSL) are evaluated for the 0.6 μm-pitch isolation of 256 Mbit DRAM. About 4000 Å field oxide grown in a 1100°C wet ambient is found to be optimal for field oxide thinning and bird´s beak “punch-through” effects. At a given pad oxide thickness of 100 Å the end-of-line encroachment is the largest for MSL isolation, which essentially rules out MSL as a possible candidate. Although both SSMSL and RSSMSL have similarly good isolation characteristics and diode leakages, only RSSMSL has the undesirable subthreshold double-hump effect and reduced gate oxide integrity, both of which are due to the sharp corners associated with the silicon recess etch of the RSSMSL structure. Therefore, for the three structure studied, only SSMSL is a viable candidate for the 0.6 μm-pitch isolation of 256 Mbit DRAM
Keywords :
CMOS memory circuits; DRAM chips; integrated circuit technology; isolation technology; 0.6 micron; 1100 C; 256 Mbit; 4000 A; DRAM fabrication; LOCOS-type isolation; Si; Si recess etch; diode leakage; dynamic RAM; field oxide; modified scaled LOCOS; recessed SSMSL; sidewall sealed MSL; CMOS logic circuits; CMOS technology; Etching; Instruments; Isolation technology; Leakage current; Random access memory; Semiconductor diodes; Silicon; Stress;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-2773-X
DOI :
10.1109/VTSA.1995.524628