An Integrated 60-GHz Front-end Receiver with a Frequency Tripler Using 0.13-μm CMOS Technology

Author

Chen, Po-Hung ; Chen, Min-Chiao ; Wu, Chung-Yu

Author_Institution

Nat. Chiao Tung Univ., Hsinchu

fYear

2007

fDate

11-14 Dec. 2007

Firstpage

829

Lastpage

832

Abstract

In this paper, a 60-GHz CMOS direct-conversion receiver integrated with a frequency tripler is proposed. The proposed receiver consists of a low-noise amplifier (LNA), a down-conversion mixer, output buffers, and a frequency tripler. This chip is designed using 0.13-um CMOS technology. By using a frequency tripler, the operating frequency of the PLL can be reduced from 60 GHz to 20 GHz. This makes the implementation of the PLL much easier. According to the simulation results, the receiver has a noise figure (NF) of 7.6 dB, a power gain of 29.2 dB. It consumes 14.2 mW from a 1.2- V power supply.

Keywords

CMOS integrated circuits; buffer circuits; frequency multipliers; low noise amplifiers; mixers (circuits); phase locked loops; receivers; CMOS direct-conversion receiver; CMOS technology; PLL; down-conversion mixer; frequency tripler; front-end receiver; low-noise amplifier; noise figure; operating frequency; output buffers; power gain; power supply; CMOS technology; Circuits; Energy consumption; Frequency; Millimeter wave technology; Noise figure; Parasitic capacitance; Performance gain; Phase locked loops; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on

Conference_Location

Marrakech

Print_ISBN

978-1-4244-1377-5

Electronic_ISBN

978-1-4244-1378-2

Type

conf

DOI

10.1109/ICECS.2007.4511119

Filename

4511119