DocumentCode
3364768
Title
Suppressed boron penetration in P+-poly PMOSFETs with NO-nitrided SiO2 gate dielectrics
Author
Han, L.K. ; Wristers, D. ; Chen, T.S. ; Lin, C. ; Chen, K. ; Fulford, J. ; Kwong, D.L.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear
1995
fDate
31 May-2 Jun 1995
Firstpage
36
Lastpage
39
Abstract
Ultrathin NO-nitrided SiO2 has been demonstrated to be a promising gate dielectric for dual-gate CMOS to alleviate the boron penetration problem in BF2-implanted polysilicon gated p-MOSFETs. Results indicate that for both n+-poly n-MOSFETs and p+-poly p-MOSFETs, devices with NO-nitrided SiO2 gate dielectrics exhibit superior electrical characteristics as well as device reliability as compared to those with control SiO2
Keywords
MOSFET; dielectric thin films; diffusion barriers; nitridation; nitrogen compounds; semiconductor device reliability; silicon compounds; NO-SiO2; device reliability; dual-gate CMOS; electrical characteristics; gate dielectrics; n+-poly n-MOSFETs; nitridation; p+-poly p-MOSFETs; suppressed boron penetration; Annealing; Boron; CMOS technology; Capacitance-voltage characteristics; Degradation; Dielectric devices; Electric variables; MOS capacitors; MOSFET circuits; Thickness control;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on
Conference_Location
Taipei
ISSN
1524-766X
Print_ISBN
0-7803-2773-X
Type
conf
DOI
10.1109/VTSA.1995.524629
Filename
524629
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