DocumentCode :
3364817
Title :
Security-centric FPGA CAD tools to balance dual-rail routing INWDDL designs
Author :
Amouri, Emna ; Marrakchi, Zied ; Mehrez, Habib
Author_Institution :
LIP6, Univ. Pierre et Marie Curie, Paris, France
fYear :
2011
fDate :
13-15 April 2011
Firstpage :
191
Lastpage :
196
Abstract :
The Wave Dynamic Differential Logic (WDDL) is considered as a relevant hardware countermeasure to increase the robustness of cryptographic devices against Differential Power Attacks (DPA). However, to guarantee its effectiveness, the routing in both the direct and complementary paths must be balanced, to obtain equal propagation delays and power consumption on differential signals.
Keywords :
cryptography; delays; field programmable gate arrays; logic CAD; network routing; timing; trees (mathematics); DPA; PathFinder router; WDDL design; cryptographic device; differential power attacks; dual-rail routing tool; mesh FPGA; placement tool; power consumption; propagation delay; security-centric FPGA CAD tool; switch delays; timing unbalance problem; timing-balance driven router; tree FPGA; wave dynamic differential logic design; wire delays; Computer architecture; Delay; Field programmable gate arrays; Routing; Switches; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Programmable Logic (SPL), 2011 VII Southern Conference on
Conference_Location :
Cordoba
Print_ISBN :
978-1-4244-8847-6
Type :
conf
DOI :
10.1109/SPL.2011.5782647
Filename :
5782647
Link To Document :
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