• DocumentCode
    3364892
  • Title

    A reconfigurable GF(2M) elliptic curve cryptographic coprocessor

  • Author

    Morales-Sandoval, M. ; Feregrino-Uribe, C. ; Cumplido, R. ; Algredo-Badillo, I.

  • Author_Institution
    Polytech. Univ. of Victoria, Ciudad Victoria, Mexico
  • fYear
    2011
  • fDate
    13-15 April 2011
  • Firstpage
    209
  • Lastpage
    214
  • Abstract
    Elliptic Curve Cryptography (ECC) is a kind of cryptography that provides the security information services using shorter keys than other known public-key crypto-algorithms without decreasing the security level. This makes ECC a good choice for implementing security services in constrained devices, like the mobile ones. However, the diversity of ECC implementation parameters recommended by international standards has led to interoperability problems among ECC implementations. This work presents the design and implementation results of a novel FPGA coprocessor for ECC than can be reconfigured at run time to support different implementation parameters and hence, different security levels. Regardless there are several related works in the literature, to our knowledge this is the first ECC coprocessor that makes use of a partial reconfigurable methodology to deal with interoperability problems in ECC. A suitable application of the proposed reconfigurable coprocessor is the security protocol IPSec, where the domain parameters for ECC-based cryptographic schemes, like digital signature or encryption, have to be negotiated and agreed upon by the communication partners at run time.
  • Keywords
    Galois fields; coprocessors; digital signatures; field programmable gate arrays; public key cryptography; reconfigurable architectures; ECC coprocessor; ECC-based cryptographic scheme; FPGA coprocessor; IPSec; digital signature; encryption; public-key crypto-algorithms; reconfigurable GF(2M) elliptic curve cryptographic coprocessor; security information services; security protocol; Coprocessors; Elliptic curve cryptography; Elliptic curves; Field programmable gate arrays; Hardware; Program processors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Programmable Logic (SPL), 2011 VII Southern Conference on
  • Conference_Location
    Cordoba
  • Print_ISBN
    978-1-4244-8847-6
  • Type

    conf

  • DOI
    10.1109/SPL.2011.5782650
  • Filename
    5782650