VLSI implementation of early branch prediction circuits for high performance computing

Author

Farooqui, Aamir A. ; Oklobdzija, Vojin G.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

fYear

1999

fDate

4-6 Mar 1999

Firstpage

30

Lastpage

33

Abstract

In this paper, design and VLSI implementation of an Early Branch Prediction (EBP) circuit, based on a variation of the Carry Look-ahead scheme is presented. The key features of this design are low area, high speed (2 [log n/2]+1), and high modularity. This design out performs all the EBP designs presented so far. For 64-bit word length the early branch prediction is obtained in 679 ps as simulated for 0.2 μm technology under typical conditions. Simulation and layout results for 0.2 μm CMOS technology show a 30% increase in speed with 25% decrease in area as compared, to recently published results

Keywords

CMOS logic circuits; VLSI; high-speed integrated circuits; integrated circuit design; logic design; 0.2 micron; 64 bit; CMOS technology; VLSI implementation; carry look-ahead scheme; early branch prediction circuits; high modularity; high performance computing; high speed operation; low area design; Circuit synthesis; Delay; Ear; High performance computing; Reactive power; Testing; Very large scale integration; World Wide Web;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Conference_Location

Ypsilanti, MI

ISSN

1066-1395

Print_ISBN

0-7695-0104-4

Type

conf

DOI

10.1109/GLSV.1999.757370

Filename

757370