CAD methodology for Analog Static CMOS Design Automation

The computer-aided design (CAD) methodology proposed in this paper, automates analog static CMOS design. This methodology is based on the EKV model which is continuous over the inversion range. This methodology provides accurate description of current drain (error ≪ 10%) with integration of second order effects in charts for simplicity. It explores the whole solution space. Thus, circuits are sized without inversion level constraint and can be optimized unambiguously for given design requirements and given technology. The methodology is illustrated on a classic self-biased compact current reference. The circuit is optimized in supply voltage. The simulation in 0.15¿m technology gives a minimum supply voltage of 800mV for a current target of 50nA with 10% accuracy.