A dynamic buffer resize technique for networks-on-chip on FPGA

Networks-on-chip have a relative area and delay overhead compared to buses. These can be improved in application specific systems where heterogeneous communication infrastructures provide high bandwidth in a localized fashion and reduce underutilized resources. However, for general purpose architectures, design time techniques are not efficient. One approach for improving area and/or performance of NoCs for general purpose systems is to consider dynamic adaptation of the resources at runtime. In this paper, we analyze the buffer resize approaches applied to FPGA and propose a buffer resize technique. The results show that the technique improves the area and the performance of the architecture on FPGA but is less efficient than ASIC implementations.