A high data rate BPSK receiver implementation in FPGA for high dynamics applications

Author

Maya, Juan Augusto ; Casco, Nicolás A. ; Roncagliolo, Pedro A. ; García, Javier G.

Author_Institution

Area de Transferencia de Tecnol., Inst. Argentino de Radioastronom., Buenos Aires, Argentina

fYear

2011

fDate

13-15 April 2011

Firstpage

233

Lastpage

238

Abstract

In this paper we present the implementation of a FPGA based high data rate BPSK receiver specifically designed to withstand the high dynamics of airborne vehicles (i.e. aircraft, sounding rockets, satellites, etc.). The carrier recovery is implemented through a Costas loop, and a Gardner detector is used for the timing recovery. This architecture was chosen because it provides almost independent carrier and bit synchronization. Loop filters were designed through analog to discrete-time conversion. A theoretical analysis of the design, simulation and its implementation is presented.

Keywords

analogue-digital conversion; avionics; field programmable gate arrays; filters; phase shift keying; radio receivers; wireless channels; Costas loop; FPGA; Gardner detector; airborne vehicles; almost independent carrier; analog to discrete time conversion; bit synchronization; carrier recovery; high data rate BPSK receiver; high dynamics application; loop filter; timing recovery; Detectors; Field programmable gate arrays; Noise; Receivers; Timing; Vehicle dynamics; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Programmable Logic (SPL), 2011 VII Southern Conference on

Conference_Location

Cordoba

Print_ISBN

978-1-4244-8847-6

Type

conf

DOI

10.1109/SPL.2011.5782654

Filename

5782654