Title :
New 2 Gbit/s CMOS I/O pads
Author :
Masera, Guido ; Piccini, G. ; Roch, Massimo Ruo ; Zamboni, Maurizio
Author_Institution :
Dipt. di Elettronica, Torino Univ., Italy
Abstract :
A couple of low complexity high performance input and output pads are proposed: they have been designed in 0.7 μm CMOS ES2 technology and support bit rates ranging from DC up to 2 Gbit/s. The differential input pad and the differential output pad interface true PECL external logic levels to full swing 5 V CMOS internal levels
Keywords :
CMOS digital integrated circuits; VLSI; integrated circuit layout; 0.7 micron; 2 Gbit/s; 5 V; CMOS ES2 technology; CMOS I/O pads; PECL external logic levels; bit rates; differential input pad; differential output pad; full swing 5 V CMOS internal levels; high performance pads; layouts; low complexity pads; Atherosclerosis; Bonding; CMOS logic circuits; CMOS technology; Capacitance; Electrostatic discharge; Frequency; Impedance matching; Mirrors; Voltage;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757382
