• DocumentCode
    336500
  • Title

    Hierarchical scheduling in high level synthesis using resource sharing across nested loops

  • Author

    Ghosh, Abhijit ; Lodha, Sandeep K. ; Vemuri, Ranga

  • Author_Institution
    Dept. of Electron. Comput. & Eng. Comput. Sci., Cincinnati Univ., OH, USA
  • fYear
    1999
  • fDate
    4-6 Mar 1999
  • Firstpage
    140
  • Lastpage
    143
  • Abstract
    This paper presents a resource-constrained scheduling algorithm for hierarchical behavioral specifications containing nested loops. The algorithm attempts to share resources across levels, to schedule operations that belong to different levels of the nested loop structures in the specifications as well as operations that belong to the same level. We compare the results of scheduling using our algorithm with those obtained using traditional list scheduling with no sharing of resources among different levels of the specification. These results show an average improvement of 23.47% in terms of number of control steps
  • Keywords
    VLSI; data flow graphs; high level synthesis; scheduling; control steps; hierarchical scheduling; high level synthesis; nested loops; resource sharing; resource-constrained scheduling algorithm; Algorithm design and analysis; High level synthesis; Resource management; Scheduling algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
  • Conference_Location
    Ypsilanti, MI
  • ISSN
    1066-1395
  • Print_ISBN
    0-7695-0104-4
  • Type

    conf

  • DOI
    10.1109/GLSV.1999.757396
  • Filename
    757396